Design Engineer

•    Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.
•    Should have worked on 65nm / 45nm / 28nm process technologies .
•    Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
•    Good handle on IR/EM related issues in memory layouts.
•    Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
•    Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
•    Experience & or strong interest in memory compilers developed.
•    Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.

Memory layoutMemory compilerfinfetSRAM compilerSRAM Layout14nm

Education:UG -B.Tech/B.E. - Any Specialization, Other Graduate
PG - Other
Doctorate - Doctorate Not Required, Any Doctorate - Any Specialization
Sankalp Semiconductors is the preferred choice for analog mixed signal services and solutions specializing in end to end solutions for IO's, analog and mixed signal chip design and layout. Our analog and mixed signal expertise combined with the SoC design capabilities makes us a one stop destination for all our customers. Sankalp Semiconductors was founded in 2005 by a team of industry experts with a mission to create a world class technology hub of mixed signal services and solutions. The company has today more than 500 employees worldwide with offices in India (Bangalore, Hubli, Kolkatta, Bhubaneswar), US (Dallas, San Jose), Germany (Frankfurt) and Canada (Ottawa).The company is the recipient of several Industry accolades like Red Herring Asia, Deloitte Tech Fast 50India, STPI recognitions and quite recently was selected in the Red Herring Top 100 Global Tech companies.